​XK Silicon

Product

xkHEVC Lite (X2/K2)

- H.265/HEVC IP Core

- Main Profile

- Encoder

- 5MP@30fps@500MHz 

- X2: 500MHz@22nm

- K2: 150MHz@FPGA

- Ultra Low Area Cost

- High efficient RDO
- High accurate Rate Control
- Ultra low latency
- RTL/Netlist Avaliable
- C Model Evaluation Avaliable
xkHEVC Main (X1/K1)

- H.265/HEVC IP Core

- Main Profile

- Encoder/Decoder/Combo

- 8MP@30fps@800MHz

- X1: 800MHz@22nm

- K1: 200MHz@FPGA

- Low Area Cost

- High efficient RDO
- High accurate Rate Control
- Ultra low latency
- RTL/Netlist Avaliable
- C Model Evaluation Avaliable
PRODUCTs
xkZero (K0)

- Ultra Low Delay Video Codec IP Core

- Private Standard

- Encoder/Decoder/Combo

- <1ms End2End Video Delay

- 8MP@60fps

- 200MHz@FPGA

- Low Area Cost

- High efficient RDO
- High accurate Rate Control

- Ultra low latency

- RTL/Netlist Avaliable
- C Model Evaluation Avaliable
xkAVC Main (X3/K3)

- H.264/AVC IP Core

- Baseline/Main Profile

- Encoder/Decoder/Combo

- 8MP@30fps@800MHz

- X3: 800MHz@22nm

- K3: 200MHz@FPGA

- Low Area Cost

- High efficient RDO
- High accurate Rate Control
- Ultra low latency
- RTL/Netlist Avaliable
- C Model Evaluation Avaliable
xkJPG

- JPEG/MJPEG IP Core

- Encoder/Decoder/Combo

- User-defined Resulution

- Low Area Cost

- Ultra low latency
- RTL/Netlist Avaliable

- C Model Evaluation Avaliable

- AI based QP-MAP Opt. (option)

(Compression ratio improved 30%)

xkJPG-XS

- JPEG-XS IP Core

- Encoder/Decoder/Combo

- User-defined Resulution

- Low Area Cost

- Ultra low latency
- RTL/Netlist Avaliable
- C Model Evaluation Avaliable

xkJPG-LS

- JPEG-LS IP Core

- Encoder/Decoder/Combo

- User-defined Resulution

- Low Area Cost

- Ultra low latency
- RTL/Netlist Avaliable
- C Model Evaluation Avaliable

FPGA Demo 

Based on Xilinx ZCU102


1. H.265 Encoder Demo

2. H.265 Decoder Demo